780 hours ₹41,120 (General) (50% Off for General Students) FREE for SC/ST candidates NIELIT Bhubaneswar
Enrollment Open
EligibilityUG Diploma / 3-Year Diploma (after Class 10th) in Electronics & Communication Engineering, Electrical Engineering, Computer Science, IT, or allied branches, with minimum 1.5 years of relevant experience. Completed 2nd Year of Diploma (after Class 12th) in Electronics & Communication Engineering, Electrical Engineering, Computer Science, IT, or allied branches. NSQF Level 4 Certification in relevant disciplines with minimum 3 years of sectoral experience. NSQF Level 4.5 Certification in relevant disciplines with minimum 1.5 years of sectoral experience.
Duration780 hours
Training Fees₹41,120 (General) (50% Off for General Students) FREE for SC/ST candidates
Course Start Date02 Mar 2026
Course End Date02 Dec 2026
CoordinatorMadhusmita Mohanty
Training CentreNIELIT Bhubaneswar
LocationBhubaneswar, Odisha
NIELIT O level 'IT' NSQF
1 year ₹For SC/ST: Free NIELIT Bhubaneswar
Enrollment Open
Eligibility12th Or ITI Certificate (Two Years) after class 10 Or
ITI Certificate (One Years) after class 10 with one year of
experience post qualification. Or Successful completion of the second year of a Government recognized polytechnic engineering diploma course after class 10, Training of „O‟ Level course concurrently during the third year of the said 3 years Polytechnic engineering diploma course. The certificate of „O‟ level will be awarded only after successful completion of the polytechnic engineering diploma. Or 10th pass and certification in the immediate previous NSQF Level Qualification in relevant field. Or Relevant Qualification of immediate previous NSQF Level
with 2 Years of experience.
Duration1 year
Training Fees₹For SC/ST: Free
Course Start Date01 Jul 2026
Course End Date30 Jun 2027
CoordinatorAmol Anil Khairnar, Scientist-B
Training CentreNIELIT Bhubaneswar
LocationBhubaneswar, Odisha
NIELIT O level 'IT' NSQF
1 YEAR ₹₹For Gen/OBC: 9047-(Including all GST), For SC/ST: Free NIELIT Balasore Extension
Enrollment Open
Eligibility12th Or ITI Certificate (Two Years) after class 10 Or
ITI Certificate (One Years) after class 10 with one year of
experience post qualification. Or Successful completion of the second year of a Government recognized polytechnic engineering diploma course after class 10, Training of „O‟ Level course concurrently during the third year of the said 3 years Polytechnic engineering diploma course. The certificate of „O‟ level will be awarded only after successful completion of the polytechnic engineering diploma. Or 10th pass and certification in the immediate previous NSQF Level Qualification in relevant field. Or Relevant Qualification of immediate previous NSQF Level
with 2 Years of experience.
Duration1 YEAR
Training Fees₹₹For Gen/OBC: 9047-(Including all GST), For SC/ST: Free
EligibilityDiploma/Polytechnic/ITI(Pursuing OR Passed Out), B.E OR B.Tech (Pursuing OR Passed Out), Passed Out Graduates/Post-graduates OR Students (Pursuing OR Passed Out) Graduation/Post-Graduation degree in Science/engineering domain.
Duration6 months
Training Fees₹10000(Including GST)
Course Start Date01 Jun 2026
Course End Date15 Jun 2026
CoordinatorKaushik Mohanty,Biswajit Jena
DescriptionLocation:-NIELIT CAMPUS-II(IHM),Near Indian Overseas Bank, V.S.S. Nagar, Bhubaneswar - 751007, Odisha, India
Eligibility2 Years of 3-Years Diploma in Electronics and Communication Engineering/ Electrical Engineering/CS/IT and allied branches after class 10th, B.Tech/M.Tech in Electronics and Communication Engineering/ Electrical Engineering/CS/IT and allied branches. B.Sc/M.Sc in Electronics/CS/IT or related fields.
Duration120 hours / 1 Month
Training Fees₹5900 (Including GST)
Course Start Date01 Jun 2026
Course End Date20 Jul 2026
CoordinatorMadhusmita Mohanty (7978702743)
DescriptionFPGA Prototyping Using Verilog HDL is a hands-on course that introduces the design, simulation, and implementation of digital systems on FPGA platforms using Verilog Hardware Description Language (HDL). Students learn FPGA architecture, combinational and sequential logic design, finite state machines (FSMs), synthesis, timing analysis, and hardware debugging through practical projects and laboratory exercises. The course provides the skills required for FPGA-based embedded systems, digital design, and hardware prototyping applications.